AMD’s Zen 4 I/O Die Detailed Courtesy of ISSCC Presentation

Although we’ve known most of the details of AMD’s I/O die in its Zen 4 processors, until now, AMD hadn’t shared a die shot of the cIOD, but thanks to its ISSCC 2023 presentation, we not only have a die shot of the cIOD, but some friendly people on the internet have also made annotations for us mere mortals. There are no big secrets here, but based on the annotations by @Locuza_ we now know for certain that it’s not possible to use the current I/O die with three CCDs, as it only has two GMI3 interfaces, to which the CCDs are connected.

If you’re wondering about the 2x 40-bit memory interface, it’s for ECC memory support outside of the on-die ECC support of DDR5 memory. Also note that DDR5 memory is two times 32-bit in non ECC mode. That said, it’s up to the motherboard makers to implement support for ECC memory, but it would appear all Zen 4 CPUs support it. The addition of a GPU, even a basic one like this, takes up a fair bit of space inside the cIOD, especially once you add things like video decoders/encoders and so on. In fact, it appears that the parts related to the GPU and video decoders/encoders take up at least a third of the space inside the I/O die, yet thanks to a significant die shrink from the Zen 3 era cIOD, it’s physically smaller in the Zen 4 processors, while having an estimated 58 percent increase in transistors.